lukechampine
212 lines
3.3 KiB
ArmAsm
212 lines
3.3 KiB
ArmAsm
// +build amd64,!gccgo,!appengine,!nacl
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#include "textflag.h"
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#define Dst DI
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#define A R8
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#define B R9
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#define N R12
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// func xorBytesSSE(dst, a, b []byte, n int)
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TEXT ·xorBytesSSE(SB),NOSPLIT,$0
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MOVQ dst_data+0(FP), Dst
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MOVQ a_data+24(FP), A
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MOVQ b_data+48(FP), B
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MOVQ n+72(FP), N
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XOR_LOOP_128_SSE:
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CMPQ N, $128
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JB XOR_LOOP_64_SSE
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MOVOU (A), X0
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MOVOU 16(A), X1
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MOVOU 32(A), X2
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MOVOU 48(A), X3
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MOVOU 64(A), X4
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MOVOU 80(A), X5
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MOVOU 96(A), X6
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MOVOU 112(A), X7
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PXOR (B), X0
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PXOR 16(B), X1
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PXOR 32(B), X2
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PXOR 48(B), X3
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PXOR 64(B), X4
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PXOR 80(B), X5
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PXOR 96(B), X6
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PXOR 112(B), X7
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MOVOU X0, (Dst)
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MOVOU X1, 16(Dst)
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MOVOU X2, 32(Dst)
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MOVOU X3, 48(Dst)
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MOVOU X4, 64(Dst)
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MOVOU X5, 80(Dst)
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MOVOU X6, 96(Dst)
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MOVOU X7, 112(Dst)
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ADDQ $128, A
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ADDQ $128, B
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ADDQ $128, Dst
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SUBQ $128, N
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JNZ XOR_LOOP_128_SSE
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RET
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XOR_LOOP_64_SSE:
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CMPQ N, $64
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JB XOR_LOOP_16_SSE
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MOVOU (A), X0
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MOVOU (B), X1
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MOVOU 16(A), X2
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MOVOU 16(B), X3
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MOVOU 32(A), X4
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MOVOU 32(B), X5
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MOVOU 48(A), X6
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MOVOU 48(B), X7
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PXOR X0, X1
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PXOR X2, X3
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PXOR X4, X5
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PXOR X6, X7
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MOVOU X1, (Dst)
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MOVOU X3, 16(Dst)
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MOVOU X5, 32(Dst)
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MOVOU X7, 48(Dst)
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ADDQ $64, A
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ADDQ $64, B
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ADDQ $64, Dst
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SUBQ $64, N
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JNZ XOR_LOOP_64_SSE
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RET
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XOR_LOOP_16_SSE:
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CMPQ N, $16
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JB XOR_LOOP_FINAL_SSE
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MOVOU (A), X0
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MOVOU (B), X1
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PXOR X0, X1
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MOVOU X1, (Dst)
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ADDQ $16, A
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ADDQ $16, B
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ADDQ $16, Dst
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SUBQ $16, N
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JNZ XOR_LOOP_16_SSE
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RET
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XOR_LOOP_FINAL_SSE:
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MOVB (A), AL
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MOVB (B), BL
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XORB AL, BL
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MOVB BL, (Dst)
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INCQ A
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INCQ B
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INCQ Dst
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DECQ N
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JNZ XOR_LOOP_FINAL_SSE
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RET
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// func xorBytesAVX(dst, a, b []byte, n int)
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TEXT ·xorBytesAVX(SB),NOSPLIT,$0
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MOVQ dst_data+0(FP), Dst
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MOVQ a_data+24(FP), A
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MOVQ b_data+48(FP), B
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MOVQ n+72(FP), N
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XOR_LOOP_128_AVX:
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CMPQ N, $128
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JB XOR_LOOP_64_AVX
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VMOVDQU (A), X0
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VMOVDQU 16(A), X1
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VMOVDQU 32(A), X2
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VMOVDQU 48(A), X3
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VMOVDQU 64(A), X4
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VMOVDQU 80(A), X5
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VMOVDQU 96(A), X6
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VMOVDQU 112(A), X7
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VPXOR (B), X0, X0
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VPXOR 16(B), X1, X1
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VPXOR 32(B), X2, X2
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VPXOR 48(B), X3, X3
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VPXOR 64(B), X4, X4
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VPXOR 80(B), X5, X5
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VPXOR 96(B), X6, X6
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VPXOR 112(B), X7, X7
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VMOVDQU X0, (Dst)
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VMOVDQU X1, 16(Dst)
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VMOVDQU X2, 32(Dst)
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VMOVDQU X3, 48(Dst)
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VMOVDQU X4, 64(Dst)
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VMOVDQU X5, 80(Dst)
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VMOVDQU X6, 96(Dst)
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VMOVDQU X7, 112(Dst)
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ADDQ $128, A
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ADDQ $128, B
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ADDQ $128, Dst
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SUBQ $128, N
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JNZ XOR_LOOP_128_AVX
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RET
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XOR_LOOP_64_AVX:
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CMPQ N, $64
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JB XOR_LOOP_16_AVX
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MOVOU (A), X0
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MOVOU 16(A), X1
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MOVOU 32(A), X2
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MOVOU 48(A), X3
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VPXOR (B), X0, X4
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VPXOR 16(B), X1, X5
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VPXOR 32(B), X2, X6
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VPXOR 48(B), X3, X7
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VMOVDQU X4, (Dst)
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VMOVDQU X5, 16(Dst)
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VMOVDQU X6, 32(Dst)
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VMOVDQU X7, 48(Dst)
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ADDQ $64, A
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ADDQ $64, B
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ADDQ $64, Dst
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SUBQ $64, N
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JNZ XOR_LOOP_64_AVX
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RET
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XOR_LOOP_16_AVX:
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CMPQ N, $16
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JB XOR_LOOP_FINAL_AVX
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MOVOU (A), X0
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VPXOR (B), X0, X1
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VMOVDQU X1, (Dst)
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ADDQ $16, A
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ADDQ $16, B
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ADDQ $16, Dst
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SUBQ $16, N
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JNZ XOR_LOOP_16_AVX
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RET
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XOR_LOOP_FINAL_AVX:
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MOVB (A), AL
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MOVB (B), BL
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XORB AL, BL
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MOVB BL, (Dst)
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INCQ A
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INCQ B
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INCQ Dst
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DECQ N
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JNZ XOR_LOOP_FINAL_AVX
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RET
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#undef Dst
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#undef A
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#undef B
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#undef N
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